发明名称 CAPACITOR MEMORY CIRCUIT
摘要 PURPOSE:To obtain a continuous analog output with a low-speed circuit element, by inputting the preceding signal, which remains in a feedback capacitor and is read out to an independently provided capacitor, to an operational amplifier by a switch and erasing the preceding signal. CONSTITUTION:In the initial stage of a basic clock (k), a signal eout of an output 8 is held as a preceding signal eer in a capacitor 11 through a switch 10 by a pulse phi1r of adigital control signal 12. In the latter half of the clock (k), only pulses phi2i and phi2r of digital control signals 7-i and 12 become high-level. Since the capacity of the capacitor 11 is equal to that of a capacitor 9, the discharge from the capacitor 11 neutralizes and erases the preceding signal as shown by the dotted line in figure eout. Meanwhile, the discharge from a capacitor 3i raises the voltage of the output 8 by a voltage, which is obtained by multiplying the voltage stored in the capacitor 3i by the capacity ratio of the capacitor 3i to the capacitor 9 and inverting the result of this multiplication, as shown by the broken line in figure eout. Consequently, the voltage read out to the output 8 is held during the period of one basic clock until the pulse phi2r of the signal 12 becomes high-level between a basic clock k+1 and a basic clock k+2.
申请公布号 JPS57191898(A) 申请公布日期 1982.11.25
申请号 JP19810076505 申请日期 1981.05.22
申请人 HITACHI SEISAKUSHO KK 发明人 MATSUI KAZUMASA;MATSUURA TATSUJI
分类号 G11C27/00;G11C27/02 主分类号 G11C27/00
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