发明名称 FRAME PULSE PHASE MATCHING SYSTEM IN TIME DIVISION SWITCH
摘要 PURPOSE:To arbitrality set the length of a call information line between a distributor and a time division switch device, by generating the amount of delay required in a time division switch device through the setting of the initial value of a memory access counter. CONSTITUTION:Call information 0, a frame pulse 1, and a clock pulse 2 from a distributor (not shown) are applied to a phase matching circuit 4 via a call information line G and the phase is corrected. A write access counter 9 is set to zero with a frame pulse 1' and counts a clock pulse 3 synchronized with the time slot width. The output acts like a write address of a channel memory 6 and a call information 0' is written in the memory 6 via a serial parallel conversion circuit 5. In a read access counter 11, the initial value determining the amount of delay is set with the frame pulse 1', then the clock 3 is sequentially counted and the call information in the memory 6 is read out via a storage memory 10.
申请公布号 JPS57185788(A) 申请公布日期 1982.11.16
申请号 JP19810070471 申请日期 1981.05.11
申请人 NIPPON DENKI KK 发明人 HOSAKA KANSHIN;KAMEYAMA HIDEO
分类号 H04Q11/04;(IPC1-7):04Q11/04 主分类号 H04Q11/04
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