发明名称 LOGIC ANALYZER
摘要 PURPOSE:To enable the simultaneous indication of a large number of timing wave forms, by a method wherein a means of storing logic signals to be measured and a means for displaying a straight line are mounted to modulate of the straight line of the display means in brilliance corresponding to a signal from the memory means. CONSTITUTION:Logic signals to be measured from a plural number of channels CH are compared with a predetermined threshold level by a comparision circuit 2 to store them in a randam access memory 9, and it is supplied as a series signal to a display means 20 via a position controller 15 and an OR gate 19 by means of a multiplexer 12. Switches 3, 17 and 18 are set to a contact (a), and switches 8 and 10 to a contact (b) to carry out a timing display by modulating in brilliance of a straight line. This permits a region in a direction of a Y-axis to be substantially narrowed, and enables a large number of channels to be displayed simultaneously.
申请公布号 JPS57184978(A) 申请公布日期 1982.11.13
申请号 JP19820029475 申请日期 1982.02.25
申请人 SONII TEKUTORONIKUSU KK 发明人 MACHINAGA KINICHI
分类号 G01R19/165;G01R13/28;G06F11/25 主分类号 G01R19/165
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