| 摘要 |
<p>A method is described of manufacturing Josephson junction integrated circuit devices. The method includes depositing and patterning a superconducting layer (S1) to provide both an electrode for one or more Josephson junctions and a ground plane for the whole device. The ground plane will generally be patterned to form at least one island (17, 18) which constitutes the lower electrode of a Josephson junction, and will preferably be removed where contact pads are to be formed. The upper electrodes of the junctions are constituted by a second superconducting layer (S2). Some of the Josephson junctions are of large area, so that their critical currents are such as to remain at zero volts in operation, so providing direct connection between the superconducting layers. Two such large-area junctions may be used to form a cross-over.
<??>In a convenient method of manufacture, the ground-plane layer (S1), a barrier layer (B), and a second superconducting layer (S2) may be formed consecutively so as to constitute a tri-layer (S1-B-S2), and this tri-layer may then be patterned and anodised to form a ground-plane layer and the various Josephson junctions (30-35) with their upper and lower electrodes.</p> |
