| 摘要 |
Due to a control engineering context, write and read pulse frames of time-slot multiplexers of different switching matrix stages in a multi-stage, time-division multiplex switching matrix network exhibit coinciding pulse frame boundaries. In deviation therefrom, pulse frame boundaries of the pulse frames on switching network internal time-division multiplex lines are offset due to delays that are caused by serial-to-parallel and parallel-to-serial conversions of a partial information upon their intermediate storage in the time-slot multiplexer. Of two complete memories per time-slot multiplexer, one part of the one memory and another part of the other memory are inscribed during the pulse frame of an incoming time-division multiplex line. Auxiliary information is derived from an address (corresponding to the outgoing time channel) serving for the selection of a holding memory and form an address (corresponding to the incoming time channel) assigned for reasons of switching engineering and serving for the selection of a complete memory, the auxiliary information indicating from which of the complete memories the information to be forwarded is to be read so that, given multi-channel connection, the required sequence of the partial information is assured. |
