| 摘要 |
PURPOSE:To realize a high-speed operation, by obtaining a binary code corresponding to the shift frequency necessary for the normalization of a mantissa part and then performing the shifting in a machine cycle. CONSTITUTION:It is supposed that the numerical data, i.e., an arithmetic result is stored in a register 11 in the form of ''00011010''. Thus output signals S0-S7 are generated from an upper digit detecting circuit 12 and in accordance with the signal supplied from the register 11. In this case, only the signal S3 is ''1'' among the output signals, and the residual signals are all ''0''. This means that the 3rd digit is an upper digit of the numerical data comprising an effective figure ''1'' in case the highest digit MSB of a mantissa part is set at standard ''0''. As a result, the signal ''1'' is supplied to the gate of an MOS transistor 14 of the 4th column to which the signal S3 is supplied, and a binary code ''011'' corresponding to the 3rd digit is delivered to a register 15. |
