| 摘要 |
PURPOSE:To achieve a delay time adjusting circuit with high accuracy, by incorporating a voltage controlled delay circuit inputting a clock having equal clock with a specified delay time to a phase locked loop. CONSTITUTION:A clock oscillator 1 generting a clock having a period equal to a specified delay time is connected to an input point A of a VCD2. A phase locked loop is constituted by connecting a phase comparator 3, a charge pump circuit 4, a low pass filter 5, a DC amplifier 6 and a voltage fixing circuit 7, to the input point A and an output point B of the VCD2. If the clock frequency f1 at the point A and a clock frequency f2 at the point B are shifted, an output is given to the phase comparator 3 and a control voltage for the VCD2 is generated from the DC amplifier 6. The output of the DC amplifier 6 is constant when the phase of the f1 and f2 is equal and a fixed output is applied to the VCD2 with the circuit 7. Thus, a clock output with a specified delay can be obtained at the point B. |
