| 摘要 |
PURPOSE:To enable the connection of a poly Si lead-out electrode and an Al bit line without the medium of a wiring contact window and to lessen the area of the connection part of the bit line and a drain region by a method wherein an SiC layer having a large etching resistance is provided on the lead-out electrode from the drain region. CONSTITUTION:Electrodes 4a and 4b consisting of conductive poly Si ar provided on a P-type Si substrate 1 through a thin gate SiO2 film 3, these are used as word lines and the surfaces of these electrodes are covered with an SiO2 film 7a. Then, an N<+>-type drain region 5 and N<+>-type source regions 6 are respectively formed by diffusion between these electrodes and on both sides of the electrodes using these electrodes as masks and the outer peripheries of the electrodes are encircled with an SiO2 film 7. After that, a conductive poly Si layer 9 and an SiC layer 10 are laminated and adhered on the whole surface, the layers 9 and 10 are left only between the electrodes and other parts of the layers are removed, an Al bit line 11 is adhered on the whole surface while being extendedly provided on the film 7 and this is abutted on the layer 10. In such a way, the wiring interval of the bit line is made smaller and the integration degree of a memory is enhanced.
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