发明名称 DATA TRANSFER SYSTEM
摘要 PURPOSE:To reduce the number of times of inspection during processing operation by omitting an inspection step for an administration unit of the prescribed size of a cash memory, by speeding data transfer. CONSTITUTION:The output of a comparator CMP is converted by an encoder ENC into a four-bit code, which is set in a register BNK together with a coincidence display bit and also held in a register STBNK. An address is transferred from a register STAR to a register LAR, simultaneously, the content of the register STAR is set by the length of a data to be stored, that is bit AD-L, to a register DLAR with an address adder INC. To a main storage device, a store address is sent from the register LAR, and data is also sent through a selector SEL. Data which have the same addresses in a cash memory and are to be stored in succeeding areas are the same administration unit in the cash memory, so only eight-byte data is sent and stored.
申请公布号 JPS57172583(A) 申请公布日期 1982.10.23
申请号 JP19810056984 申请日期 1981.04.17
申请人 FUJITSU KK 发明人 IYOTA HIDEO
分类号 G06F12/00;G06F12/02;G06F12/08 主分类号 G06F12/00
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