Equipment connection multi-master bus structure

摘要

The invention relates to an equipment connection multi-master bus structure in an arrangement with a microprocessor, a number of peripheral controllers and a main memory. One bus allocator is allocated to both the microprocessor and to each peripheral controller. Thus, the peripheral controllers also obtain the master status with respect to access to the equipment connection multi-master bus. The solution of priority problems is the responsibility of the bus allocators. A number of such arrangements can be combined via a system multi-master bus to form a multiprocessor system. <IMAGE>