| 摘要 |
<p>A processor control system for controlling items of hardware 16,17 includes pairs of processors 10,10a; 11,11a, associated with the hardware items. One processor 10, 11 of each pair operates the process or processes H1, H2 for controlling the associated hardware, whilst the other processor 10a, 11a a of each pair operates other processes P3, P4, P6, P7, P8. In the event of a fault in say the processor 10, the processes P3 and P4 are transferred to spare processors 12, 12a and the hardware control process H1 is transferred to the processor 10a. This arrangement makes more effective use of standby processing capacity.</p> |
