| 摘要 |
<p>A dynamic type semiconductor memory using MOS transistors, in which first and second booster circuits (18, 28) utilizing capacitances, respectively, are provided at each of stages preceding and succeeding to a word driver (13), respectively. Data lines (21) of the memory (20) are each provided with a voltage compensating circuit (24) for increasing a voltage for charging a memory cell to a level higher than a source voltage for being rewritten in the memory cell. A first boosting circuit (18) is operated after a word line driving pulse signal is produced. Subsequently, word driver selecting transistors are turned off, which is followed by operation of the second booster circuit (28). Thus, the word line voltage is boosted twice.</p> |
