| 摘要 |
PURPOSE:To increase the efficiency of data transfer and buffer management, by shortening the bit length of an address specifying a buffer block, in the buffer management of a processor. CONSTITUTION:When a memory address by an address designation line 33 does not designate the 1st and 2nd registers 23-25, a comparison circuit 26 energizes a control line 51 and sets the address on the line 33 to registers 20,21 and 22. The contents of the registers 20 and 23 are compared 52, and when they are coincident, a control line 44 is energized, the least significant bit of the register 21 is discriminated with a selection circuit 53 and a control line 46 or 47 is energized. Thus, an AND gate 28 or 29 is opened, the contents of the register 24 or 25 are outputted on a line 42 and given to a memory control circuit 9. If dissident, a control line 43 is energized and the contents of the registers 20 and 22 are transmitted to the memory control circuit 9 as they are with lines 34, 42 and 36 as a memory address. |
