发明名称 FRAME PATTERN GENERATING CIRCUIT
摘要 <p>PURPOSE:To eliminate the out of synchronism in a reception section by selecting the sequence of transmission from plural fixed pattern generating circuits by means of a control counter circuit whose initial value is set optionally. CONSTITUTION:A fixed pattern generated in each fixed pattern generating circuit 1 is selected by a selection circuit 2 and outputted from an output terminal 5 as a frame pattern. A setting circuit 4 generates an address of a frame pattern which would have been sent at present but for the package exchange depending on the time used for the exchange with a frame pattern sent just before the package exchange in the package exchange within a protection time of a frame period circuit of the reception section and gives its address to a control counter circuit 3. Then the counter circuit 3 controls the selection circuit 2 to control the order of the fixed pattern. Thus, the out of synchronism in the reception section is avoided.</p>
申请公布号 JPS63123242(A) 申请公布日期 1988.05.27
申请号 JP19860269261 申请日期 1986.11.12
申请人 NEC CORP 发明人 SHIROMIZU YASUBUMI
分类号 H03K5/156;H04J3/06;H04L7/08 主分类号 H03K5/156
代理机构 代理人
主权项
地址