| 摘要 |
PURPOSE:To set a processor at the cycle time of a high speed, by setting the request effective signal to a control pipe just through one chip cross and transmitting the signal in a speed higher than conventional. CONSTITUTION:The port parts of control circuit units 10A and 10B hold an operation OPC given from an CPU, a request effective signal REQV, address signals B and A plus a bank busy signal BB given from a memory control unit MCU respectively. An operation code converter 12a, a bank busy checker 14a, etc. are provided just in the number equivalent to a system. As a result, gates 22a and 24a, etc. which are opened/closed by the selection signal SS are provided to allow or inhibit the transmission of the above-mentioned signals OPC and BA. The signal REQV which is necessary for the decision of priority and given from another desired CPU are transferred to the control circuit of the remote side via inter-links l1 and l2. |
