发明名称 MIS TYPE SEMICONDUCTOR MEMORY DEVICE
摘要 PURPOSE:To prevent the generation of short-circuit accidents among word lines by a residue layer of a second layer polycrystalline silicon layer by dividing a first layer polycrystalline silicon layer into blocks and forming it so as to be isolated at every memory cell in the direction of bit lines and so as not to simultaneously cross two or more of adjacent word lines in the direction of word lines. CONSTITUTION:A first layer polycrystalline silicon layer forming a capacitance electrode is isolated into blocks and shaped so as to be isolated at every memory cell in the direction of bit lines 7a, 7b as shown in 4a and 4b and so as not to simultaneously cross adjacent word lines in the direction of word lines 6a-6d. Since the first layer polycrystalline silicon layer is parted between adjacent two word lines, a residue layer generated when a second layer polycrystalline silicon layer is shaped after a pattern to 6a-6d is also brought to a mutually divided state as shown in 10a and 10b. Accordingly, short circuits among word lines by the residual layer in the second layer polycrystalline silicon can be prevented.
申请公布号 JPS63127566(A) 申请公布日期 1988.05.31
申请号 JP19860274690 申请日期 1986.11.17
申请人 NEC CORP 发明人 NAKAMURA KUNIO
分类号 H01L27/10;H01L21/8242;H01L27/108 主分类号 H01L27/10
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