| 摘要 |
PURPOSE:To improve the reliability by detecting code errors, by using a transfer line to transfer the check bit between a main memory controller and a input and output controller to transmit an abnormal signal when abnormality is occured. CONSTITUTION:In a parity transmission/reception controlling circuit A11, a parity check bit against the transferred data from a data transmission/reception controllig circuit 1 is produced, and this is transferred to a parity transmission/ reception controlling circuit B13 in a main memory controller 9. In the parity transmission/reception controlling circuit B13, the data from a data transmission/reception controlling circuit 3 and the parity check bit from the parity transmission/reception controlling circuit A11 are received to perform the parity check. The result is treansferred to a code transmission/reception circuit 7 for correction. A code which detects errors impossible to be corrected is produced against the data sent from the data transmission/reception circuit 3 by a code transmission/reception circuit for correction 7. This code is stored in a main memory device 10 in the same manner as the code for correction. |
