发明名称 INPUT CIRCUIT
摘要 PURPOSE:To obtain an input circuit having the reduced variance of the threshold voltage, by obtaining a voltage-dividing output from a point of series connection of plural enhancement type IGFETs which are connected in series. CONSTITUTION:An enhancement (E) type IGFETE11 with its drain 11 and gate 12 connected to an input terminal is grounded via EFETs E12-E16. The point of connection between EFETs E11-E15 forming the 1st diode circuit and the EFETE16 forming the 2nd diode circuit is connected to an inverter consisting of depletion (D) type IGFETD11 and an EFETE17. The sum of the threshold voltage of the 1st and 2nd diode circuits is set larger than the power supply voltage VCC of the inverter, and at the same time the threshold voltage of the 2nd diode circuit is set smaller than the threshold voltage of the inverter. As a result, the change of the circuit threshold voltage due to the variation of the IGFET element can be reduced.
申请公布号 JPS57145437(A) 申请公布日期 1982.09.08
申请号 JP19810031694 申请日期 1981.03.05
申请人 NIPPON DENKI KK 发明人 OKUMURA KOUICHIROU
分类号 H03K19/003;H03K19/0944;H03K19/20 主分类号 H03K19/003
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