Read-only-memory with modified addressing.

摘要

1. A programmable read-only memory with N storage locations (10), arranged in L lines (12) of M words each comprising P bits (N = L x M x P), comprising k line addressing inputs and m column addressing inputs, the numbers k and m being the binary addressing bit numbers necessary for designating L lines and M columns, L line decoding gates (16), M column decoding gates (18) and P bit outputs adapted to transmit the stored information of the P storage locations at the intersection of a word line and a word column, designated respectively by a line decoding gate and a column decoding gate according to the logic levels applied to the addressing inputs, characterized in that L and/or respectively M is strictly included between 2**k-1 and 2**k (respectively 2**m-1 and 2**m ), and that a supplementary decoder (24) is provided between the line addressing inputs and/or respectively the column addressing inputs and the inputs of the line decoding gates (respectively of the column decoding gates), said decoder being adapted to transmit logic levels to the inputs of the line decoding gates (respectively of the column decoding gates), these levels corresponding : to the designation of a corresponding single line (respectively single column) for each of the L (respectively M) given addresses among the 2**k (respectively 2**m ) addresses susceptible of being received by the supplementary decoder ; to the designation of two lines (respectively columns) corresponding for each of the 2**k - L (respectively 2**m - M) remaining addresses susceptible of being received by the supplementary decoder, which correspond to fictive lines (respectively columns), the words applied to the outputs of the memory being in this case the logic sum or product of the words stored at the intersections of each designated column (respectively line) and each designated line (respectively column).