Circuit arrangement for converting input pulses into chatter-free synchronous output pulses with a pre-defined clock

摘要

In a circuit arrangement for converting interference-affected input pulses into chatter-free synchronous output pulses with a pre-defined clock, a dynamic input flip-flop (1) is set by one edge of an input pulse. Depending on the status of a clock signal from a clock-generating circuit (7), the setting output signal of the input flip-flop (1) is transmitted as a setting signal to an intermediate flip-flop (5) and output for the duration of the following complete clock half-cycle as an output signal at one output (8, 16). At the start of the clock half-cycle following the output clock half-cycle, the input flip-flop (1) and the intermediate flip-flop (5) are reset by means of a resetting circuit (9). <IMAGE>