| 摘要 |
<p>PURPOSE:To decrease the timing skew between multiphase clocks, by integrating a driving circuit group containing plural sets of driving circuits connected in parallel plus an adjustable timing generating means into a chip. CONSTITUTION:Plural driving circuit groups containing AND circuits 1i, 2i and 4i(i=0-n) plus a selecting circuit 3i put into a set are connected in parallel. A chip selection signal 10i, an address signal 201 plus a read/write controlling signal 202 are applied to the driving circuit group. when an OR signal 500 of each signal 10i is set at logic 1, an FF1 is set to deliver a timing signal 401. An AND is secured between the signals 10i and 401 through the circuit 1i, and a chip clock signal 31i is delivered. Then FF2-4 are set successively with the signal delayed by a delaying circuit 7 capable of an internal adjustment. An AND is secured by the circuits 3i, 2i and 4i respectively among the output signals of the FFs 2-4 plus signals 10i, 201 and 202. Then a chip address signal 33i, a chip clock signal 32i and a read/write controlling signal 34i are delivered successively to drive a memory device.</p> |
