| 摘要 |
<p>PURPOSE:To secure the stability of data transmission and receiving between a CPU and peripheral circuits, by giving clock pulses different from one another to the CPU, peripheral cirtuits (including a memory), and a buffer driver, respectively. CONSTITUTION:A clock pulse WE for write is generated in a clock circuit 5, and the pulse WE is applied to a flip-flop and is delayed by driving it by a reference clock CL to generate a CPU operation clock phiCPU and a clock pulse RE for read. The pulse WE is >=10 nanoseconds earlier than the clock phiCPU, and the pulse RE is >=10 nanoseconds later than the clock phiCPU. These pulses are applied individually, and thus, the pulse RE is outputted from an AND gate 8 in the data read mode where a CPU 1 reads data from a peripheral circuit, and the pulse RE and the pulse WE are combined in an OR gate 7, and the edge of the combined pulse is later than that of the clock phiCPU, and a required pulse for read is obtained.</p> |
