| 摘要 |
PURPOSE:To increase the freedom of wiring and to facilitate visual check, in designing the wiring pattern of a semiconductor device by a master slice system, by omitting unnecessary patterns. CONSTITUTION:Suppose an input NAND gate having 3 inputs and the like is used as a 2 input device in a TTL circuit. In this case, e.g., the wiring pattern 1 of standard wiring patterns 1, 2, and 3 which are to be provided for input terminals E1, E2, and E3 becomes unnecessary. When intercell wirings are automatically performed by a grid system in such a case, necessity of these wirings is checked. If it is judged that one wiring is unnecessary, generation of such an unnecessary pattern is avoided in a pattern generating program, and the unnecessary wiring is not performed. Therefore the blank grid point such as grid point (a) can be utilized for other wirings as required. |
