Time division switching circuit with time slot interchange

摘要

A time division switching circuit with time slot interchange uses an input shift register to convert one-frame binary coded input data of time division multiplex type from an incoming line into a parallel bit output. The parallel bit output undergoes gate control of a gate matrix and its bit array is statically changed to a given bit array. The on/off control of the gate at the cross point of the gate matrix is conducted according to parallel bit outputs of a plurality of control shift registers which stores predetermined contents. The one-frame bit data thus exchanged are supplied to an output shift register. They are transmitted to an outgoing line as binary coded output data of time division multiplex type.