| 摘要 |
PURPOSE:To decrease number of transistors (TRs) by using five MOS TRs based on the inverted logic in a circuit generating a logic taking priority to given two input. CONSTITUTION:Since a 2nd MOS TR 5 is turned off when the level of a 1st input signal A1 is logical '1' in a CMOS logic gate circuit, the drain potential of a 2nd PMOS TR 7 reaches a potential corresponding to the logical '1' level. Then with a 2nd input signal B1 at logical '0', a 3rd NMOS TR 6 is turned off and the 2nd PMOS TR 7 turned on, resulting that the output is logical '1'. The output signal is all logical '0' in a combination other than the 1st and 2nd input signals A1, B1, and the logic of Q1=A1.-B1 is realized and the logic giving priority to the input signal A1 is obtained. |
