| 摘要 |
PURPOSE:To correct a bit error to obtain a sure pattern coincidence detection output, by providing additionally a delay circuit, which delays the output of an OR circuit by a prescribed number of bits, in the output terminal of the OR circuit. CONSTITUTION:Delay circuits 6a-6c are provided additionally in respective output terminals of OR circuits 4a-4c, and pattern coincidence detection signals transmitted from OR circuits are delayed by n-number bits, and these delayed output signals and output signals of OR circuits 4a-4c are operated for AND by AND circuits 7a-7c to obtain pattern coincidence detection signals 8a-8c. If an one-bit error occurs on the line, the pattern coincidence detection output is zero for a time corresponding to n-number bits from the input of this bit to a shift register 2 to the output of this bit after n-bit shift, and thus, the one- bit error in receiving is detected. This error is corrected by delay circuits and OR circuits, and the coincidence detection output with the error corrected is obtained. |
