发明名称 MANUFACTURE OF J-FET
摘要 PURPOSE:To facilitate a high mutual conductance and a low capacity of a gate by ion implanting of the impurity of the same conductivity type as a source and a drain into both sides of the gate thereby reducing the length of the gate. CONSTITUTION:Semiconductors 1, 2 each having different conductivity are formed and a gate 9 of the same conductivity as the semiconductor 1, and a source and drain 8 regions having the same conductivity as the semiconductor 2 are formed. An SiO2 film 3 formed on the surface of the semiconductor 2 is removed and a new SiO2 film 3 is formed. The film 3 is coated with photo resist 11 and a hole 12 on the resist 11 is opened on the gate leaving an area corresponding to the necessary length of the gate. The impurity of the same conductity as the semiconductor 2 implanted through the hole 12 to reverse the type of conductivity of the implanted gate 9. A junction type FET having a gate 13 of reduced length 14 which contacts the semiconductor 2 is obtained.
申请公布号 JPS57120374(A) 申请公布日期 1982.07.27
申请号 JP19810005008 申请日期 1981.01.19
申请人 HITACHI DENSHI KK 发明人 MISAWA HIROSHI;TANAKA SHIYUUHEI
分类号 H01L29/80;H01L21/337;H01L29/808;(IPC1-7):01L29/80 主分类号 H01L29/80
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