| 摘要 |
PURPOSE:To correct the operating voltage of an MIS memory and to increase the manufacturing yield rate and temperature margin, by controlling a power supply voltage of a memory cell through the output of a circuit connecting resistive and active elements in series. CONSTITUTION:Memory cells 1a-1d consist of FFs comprising high resistors R1, R2 formed with poly crystal silicon layer and N channel type drive MISFETs Q1, Q2, and of N channel transfer gates Q3, Q4 provided between input/output terminals of the FF and cells, with matrix location. Further, the resistor R1 makes current supply to prevent discharge of information charge stored in the gate capacitance of the Q2 due to the drain leakage current of the Q1, and similarly the R2 makes current supply to prevent the discharge of information charge of the gate of the Q1. In this case, the current change due to the change in the resistance value of R1 and R2 is compensated by the output voltage of the power supply circuit 9. |
