发明名称 MULTIPLEX CONCENTRATOR AND ALLOTER DEVICE
摘要 PURPOSE:To lower the frequency of appearance of synchronizing characters to enhance the multiplexing degree of a trunk circuit, by transmitting and receiving data of respective low-speed lines with plural bytes corresponding to their communication speeds as units in one frame on the high-speed trunk circuit. CONSTITUTION:In case of data transfer from the center side to the terminal side, a high-speed line control part 103 of a multiplex concentrator and alloter device 4 scans low-speed circuits 102 successively and transmits data, which are stored in these circuits 102 and are received from low-speed lines 2, to a high- speed trunk circuit 6 along the format shown in figure. Meanwhile, in a concentrator and alloter device 7 in the terminal side, a high-speed line control part 104 monitors the receiving of synchronizing characters; and when detecting synchronizing characters, the control part 104 sets a counter 105 5o ''8''. Succeeding receiving data is transferred to a low-speed line channel (CH1) 106 in bit parallel each time one character is received. The counter 105 is increased by +1 each time one bit of receiving data is received; and when count contents become ''40'', the transfer destination of receiving data is switched to a channel (CH2) 106.
申请公布号 JPS57115055(A) 申请公布日期 1982.07.17
申请号 JP19810001245 申请日期 1981.01.09
申请人 HITACHI SEISAKUSHO KK 发明人 ASOU FUSAYOSHI;AKIYAMA FUMIO;MOTOHASHI TOMOO
分类号 H04J3/06;H04L12/52 主分类号 H04J3/06
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