| 摘要 |
<p>A field programmable semiconductor memory device comprises regular word lines (W), regular bit lines (B), regular memory cells (MC) connected at the intersections of the regular word lines (W) and the regular bit lines (B), at least one test word line (TW) adjacent one of the regular bit lines (B) and alternately arranged conducting (10d, 10f) and non-conducting (10c, 10e) test memory cells arranged at the intersections of the test bit lines (TB) and the regular word lines (W). To enable the insulation between adjacent word lines (W) to be tested, the test bit line (B) and the regular word line (W) are insulated from one another by an insulating layer (24) in each non-conducting test memory cell (10c, 10e).</p> |
