This negative resistance network includes a first predetermined channel insulated gate enhancement type field effect transistor having a drain-source path connected to positive and negative input terminals on which a predetermined input voltage is impressed. The gate potential of the first field effect transistor is controlled by a second insulated gate enhancement type field effect transistor having an opposite channel type to the first field effect transistor, a gate connected to the drain thereof which is connected to the predetermined one of the positive and negative input terminals and a source connected to one pole of a dc power supply having a predetermined voltage, and by a third insulated gate enhancement type field effect transistor having the same channel type as the first field effect transistor, a drain and a gate connected to the drain of the second field effect transistor as well as to the gate of the first field effect transistor and a source connected to the source thereof which is connected to the other input terminal as well as to the other pole of the dc power supply, whereby the first field effect transistor shows a negative resistance characteristic attaining a relatively low current consumption over a relatively wide level range of the input voltage.
申请公布号
DE2556683(C3)
申请公布日期
1982.07.08
申请号
DE19752556683
申请日期
1975.12.16
申请人
TOKYO SHIBAURA ELECTRIC CO., LTD., KAWASAKI, KANAGAWA, JP
发明人
AIHARA, MITSUO, TOKYO, JP;TAKADA, SHIGEHO, OOITA, JP;OGAWA, HISAHARU, YOKOHAMA, JP
