| 摘要 |
PURPOSE:To improve the reliability of the circuit, by controlling peripheral hardware of an MPU by a program to facilitate changing the range of acquisition of bit synchronization, the time of acquisition, the variation of phase correction after acquisition, etc. CONSTITUTION:When digital receiving data is inputted, a detecting circuit 2 outputs a pulse B at the fall of the signal and gives this pule B as an interruption signal to an MPU3. Meanwhile, a reference clock is divided by information of a frequency division ratio from the MPU3 in a variable frequency divider 5 and is given to a shift register 6 as a sampling clock C. The MPU3 reads the count value of the frequency divider 5 at the time when the interruption signal is given, and the MPU3 sends information of the frequency division ratio to the frequency divider 5 to control the phase of the clock C. By correcting the phase of the clock C successively in this manner, bit synchronization is acquired to sample always receiving data correctly. |
