| 摘要 |
In this successive approximation analog-to-digital converter non-precise impedance elements are used in a circuit which provides successive analog step values that approximate a non-binary series in which (above a certain minimum) each term is smaller than the sum of the preceding series terms. The actual values of the analog quantities that are produced by the corresponding individual impedance elements are stored in digital format in a memory. These quantities are measured and stored with an accuracy which exceeds the accuracy expected for the final operation of the system. At each conversion step, the unknown analog input is compared with the sum of a pair of step values, the smaller of which is greater than the maximum expected comparator error. An acceptable comparator output may be obtained before the comparator has completely settled. If the comparator output indicates that the unknown input is greater than the compared analog value, the larger term is retained for inclusion in subsequent comparison steps. The actual value of the retained term is accessed from the memory and summed in an accumulator which contains, at the end of the comparison cycle, the digital value of the analog input.
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