| 摘要 |
PURPOSE:To achieve parallel processing for a plurality of operating devices, by reducing the burden of the reception side of an output data and the supply side of an input data, through the control of the data supply to a plurality of operation devices and the output of resulting data from the operation devices at an operation processing section itself. CONSTITUTION:Input gates Pio-Pin and output gates Poo-Pon are connected to one input data register Ri and one output data register Ro respectively, and a plurality of operation devices Eo-En are connected to the input and output gates Pio-Pin and Poo-Pon. The operating data from the register Ri is inputted to the input gates Pio-Pin of operation devices Eo-En sequentially with n-cycle interval, the gates Pio-Pin are opened with the control of an input control section Ci with the corresponding cycle and operation is made at the operator devices Eo-En. In accordance with the result of operation of the operator devices Eo-En, the output gates Poo-Pon are opened by the control of an output gate control section Co, the result of operation is added to the register Ro, and parallel processing of the operator devices Eo-En of the plurality can be made. |
