| 摘要 |
PURPOSE:To enable the transmission of all mark signal required for the test for margin of sinusoidal wave superimposition, by applying a signal frequency-dividing a clock signal into two to the input of a unipolar-ternary value conversion circuit. CONSTITUTION:In performing a sinusoidal wave superimposing margin test, a switch SW is opened and an input 641 of an NAND gate 64 is at high level, then the output of NAND gate 67, 68 is always at high level. On the other hand, a clock signal synchronized with a ternary value signal is frequency-divided into two at a dioding circuit constituted with a D-FF63 to produce a noninverting frequency division signal DN and an inverting frequency division signal DI and they are applied to a unipolar-ternary value conversion circuit 62 via NAND gates 65, 66, 69, 70. Thus, to +, - signal inputs 621, 622 of the circuit 62, alternately (0, 1) and (1, 0) are inputted as (DN, DI)=(0, 1), (1, 0)... to output an all mark signal OT. |
