| 摘要 |
PURPOSE:To reduce the parasitic capacity which deteriorates the transmission characteristics of the subject integrated circuit by a method wherein the MOS circuit with which the switching of MOS capacity is performed by FET, the switching FET is shaped in a P-channel type and formed into the substrate having the prescribed low density. CONSTITUTION:The switching FET's 211-214, in the case of a switched capacitor (SC) integrator, for example, which is constituted in SMOS circuit, is made into a P-channel shape, and formed on an N type substrate 501 having the impurity density of 1X10<15>cm<-3> or below. The FET pair (211 and 212, for example) on the flat surface is arranged as follows. Al wirings 304-306 are connected to source and drain diffusion layers 301-303 through the intermediary of contact holes 307-309, and polycrystalline Si gate electrodes 310 and 311 are formed in a channel region. The junction capacitance between the diffusion layer 302 and the substrate is added to an SC capacitor 102 as a parasitic capacitance 201, and becomes the main cause of impairing transmission chracteristics, but the junction capacitance can be reduced remarkably comparing the case where it is formed as an N-channel form in P-well. Also, the fluctuation of the threshold value of the device due to the VSUB can be reduced by lowering the density. |
