| 摘要 |
PURPOSE:To contrive high integration and high speed operation for the subject semiconductor integrated circuit by a method wherein, on the gate electrode consisting of high melting point metal, an ion implanted mask, which is slightly smaller than the gate electrode, is provided and a source and drain region is formed by implantation. CONSTITUTION:A gate film 2 is formed on the FET forming region on a P type substrate 1, for example, and after an Mo film 3 and an Si nitriding film 4 have been deposited, for example, a photoetching is performed in such a manner that the films 3 and 4 will be remained on the gate region. The shape of this nitriding film pattern 4 is formed approximately 0.2-0.5mum smaller than the Mo film pattern 3 which will be used as a gate electrode. Then, through an Mo film 3, N type impurities are ion-implanted using the energy with which a little ion will reach the substrate, and a source and drain regions 5 and 6, where the lower part of the Mo film unmasked by the nitriding film 4 was formed in shallow low density, are formed. Subsequently, an interlayer film 7 and electrode wirings 8 and 9 are provided and used as an FET, and through these procedures, the shortening of the effective channel length caused by the expansion diffusion layer and the increase of a parasitic capacity can be prevented, thereby enabling to obtain a microscopically formed element which can be operated at a high speed. |
