Electronic adder and subtractor for 8421-bcd code - has facility for automatic result correction together with decimal display

摘要

The parallel adder and subtractor circuit is designed for operation in BCD-8421 code and includes an automatic facility for result correction. Each decade of adder-subtractor circuitry consists of five full adders (VA) and two half adders (VS) for the adder operation. The subtraction function is provided by five full subtractors (VS) and two half subtractors (HS). Outputs are fed to flip-flops (E,F) coupled to a decoder stage (4,5) that provide drive signals for a decimal display. The subtractend is applied to the (B) inputs and the minuend to the (A) inputs.