发明名称 IN-STEP SYNCHRONISM TYPE RECEIVING CIRCUIT
摘要 <p>PURPOSE:To simplify the circuit constitution of a timer, by constituting a timer means with a circuit which produces a gate signal with a desired time width of mono-multistable multivibrator type. CONSTITUTION:A serial signal consisting of a start bit of specified clock frequency, information bit and stop bit is inputted to a timer circuit 17, which produces a gate signal with a desired time width when it receives a pulse of the start bit. While this gate signal is produced, a timing clock generating circuit 14 produces a timing clock at reception side. The timing clock is inputted to serial parallel conversion circuit 15, which converts the serial information bit among the input signals into a parallel information bit. This information bit is outputted via a buffer memory cir cuit 16. The timer circuit 17 is constituted with a circuit of mono-multistable multi vibrator type.</p>
申请公布号 JPS5773552(A) 申请公布日期 1982.05.08
申请号 JP19800149302 申请日期 1980.10.27
申请人 NIPPON DENKI KK 发明人 YOSHIOKA TSUYOSHI
分类号 H04L7/04;H04L25/40 主分类号 H04L7/04
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