发明名称 CHANNEL BUFFER CONTROL SYSTEM
摘要 PURPOSE:To prevent the occurrence of overrun in the data transfer of a low-rank channel, by carrying out the concentrated prefetch of data in division into the high and low block numbers in priority for a channel having a large amunt of data buffer. CONSTITUTION:A data transfer request produced at a data transfer request producing circuit 7 is sent to a data request reception control circuit 4 to be accepted in the prescribed priority. Thus only for the block number having a high degree of emergency, the data are prefetched concentrically to a data buffer 9 from a main storage 1 and via a data transfer control circuit 5. For other blocks, the data are prefetched after a block is transferred to an input/output device 10 from the buffer 9. Accordingly, the data is read to the block from the storage 1 to continue the proces every time the data of a block is transmitted to the input/output device from the buffer 9.
申请公布号 JPS5773435(A) 申请公布日期 1982.05.08
申请号 JP19800148340 申请日期 1980.10.24
申请人 HITACHI SEISAKUSHO KK 发明人 SATOU TADASHI;HAYASHI KOUICHI;SASAKI AKIO
分类号 G06F5/06;G06F13/12 主分类号 G06F5/06
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