发明名称 DELAY CIRCUIT
摘要 PURPOSE:To simply obtain a wide variety of variable delay time, by forming a delay circuit through the combination of delay elements and a weighted circuit. CONSTITUTION:An input signal Vi is branched: one is multiplied with a rate (1-alpha) at a weighting circuit 6, and another is delayed with a delay element 7 in delay time T. After a delay signal from the delay element 7 is multiplied with the rate alpha at a weighting circuit 8, it is applied to an addition circuit 9, where it is added with a signal from the weighting circuit 6. Thus, the added output signal of the addition circuit 9 is delayed by a time of about alphaT to the input signal Vi by forming the delay circuit to obtain almost the same amplitude signal with the input signal Vi. Then, a wide range of variable delay time can be obtained simply by varying the rate alpha.
申请公布号 JPS5768916(A) 申请公布日期 1982.04.27
申请号 JP19800145457 申请日期 1980.10.17
申请人 FUJITSU KK 发明人 SOMEJIMA TADAHIKO;AMAMIYA SHINICHI
分类号 H03H11/26;H03H7/30;(IPC1-7):03H7/30 主分类号 H03H11/26
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