| 摘要 |
PURPOSE:To obtain data sampling clock signals without influence of noise by attaching a monostable multivibrator which is triggered at the leading edge of a sampling signal and inverted by restoration during the output of a clock line signal. CONSTITUTION:Since a flip-flop (FF) circuit 13 is reset when a sampling H singal SH is not outputted, a dividing circuit 12 is also reset. When the signal SH is outputted, the FF13 can be set up. Since a monostable multivibrator 14 is triggered, both the J and K terminals of the FF13 are turned to the ''L'' level and can not be set up by a clock line signal CR of slice data SD inputted during the ''L'' level, preventing the monostable multivibrator 14 from being set up even by a pulse-like noise before the output of the signal CR. When the reset status of the monostable multivibrator 14 is inverted by restoration, the FF13 is set up and the dividing circuit 12 starts dividing to divide an output signal S11 from an oscillator 11 and outputs a subscribed data sampling singal S12. |
