发明名称 MANUFACTURE OF GAAS INTEGRATED CIRCUIT
摘要 PURPOSE:To facilitate alignment of a microscopic mask and improve the perform ance of a planar IC, by a method wherein an alignment mark is formed on a protecting film in the process for opening windows for selective ion injection, and after active layer are formed by injecting ions, with the mark left, the protecting film is removed, and the active layers are annealed. CONSTITUTION:For example, in the process for manufacturing an IC comprising a FET of planar structure, an SiO2 film is deposited on a semiinsulative substrate, and windows are opened in the SiO2 film in order to form active layers in source, drain and channel regions by injecting ions respectively. In this first window opening process, SiO2 film patterns 22 in the number corresponding to the number of photoprocesses carried out afterward are formed at a position separate from the element region. On the other hand, the mask used in the subsequent photoprocess is provided with an alignment mark 31 positioned inward a mark 23 in a transparent region 32, for example, thereby to perform alignment. The mark 23 is not removed but left even when annealing is carried out so as to be used for alignment in, e.g., a gate electrode forming process. Thereby, it becomes unnecessary to each the substrate in order to form a mark, and substantially a capless annealing can be per formed. Accordingly, the IC can be made more microcsopic and higher in performance.
申请公布号 JPS5764921(A) 申请公布日期 1982.04.20
申请号 JP19800139773 申请日期 1980.10.08
申请人 TOKYO SHIBAURA DENKI KK 发明人 IGAWA YASUO;TOYODA NOBUYUKI;MOCHIZUKI MASAO
分类号 H01L21/265;H01L21/027;H01L21/18;H01L21/26;H01L21/266;H01L21/338;H01L29/812 主分类号 H01L21/265
代理机构 代理人
主权项
地址
您可能感兴趣的专利