发明名称 DELAY PULSE GENERATING CIRCUIT
摘要 PURPOSE:To reduce the variance in delay time against power supply voltage variance and temperature variance, by providing a clamp circuit clamping the potential of a capacitor in a delay gate circuit and driving a constant current discharge circuit with the output. CONSTITUTION:The cathode of a diode 33 in capacitive component is connected to the collector of a transistor TR24, and the anode is connected to the base of a TR 23. When an input terminal IN is at high potential H, the output H of an output point A of an amplifying gate 1 is clamped at clamp diodes 34, 36, 37-39, and the emitter of a clamped TR29 is connected to a resistor 15 constituting a constant current circuit together with the TRs 24, 25. The delay time T1 of the circuit 1 is almost equal to the product between the capacitance of the diode 33 and the resistance value of a resistor 15, and the delay time is not varied against power supply voltage variance. Further, the resistor 15 has temperature dependancy, but a resistance value R15 of the resistor 15 is not subject to temperature apparently by suitably selecting the TRs 24, 25 and a resistor 16.
申请公布号 JPS5765019(A) 申请公布日期 1982.04.20
申请号 JP19800140228 申请日期 1980.10.07
申请人 NIPPON DENKI KK 发明人 FUKUDA TERUMASA
分类号 H03K5/04;H03K5/00;H03K5/13;H03K17/28 主分类号 H03K5/04
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