| 摘要 |
PURPOSE:To ensure the high-speed reading/writing even to the data which are in the relation of multiple bit number to each other, by indicating an access to both or either one of two memories and then switching these memories. CONSTITUTION:The 1st memory 21 and the 2ns memory 22 receive an access through an even and odd address respectively. Either one of these memories 21 and 22 is selected by reading selectors 25 and 26 plus writing selectors 27 and 28. An instruction showing both or either one of the memories 21 and 22 is given to a flag 43. Then a control circuit 45 makes both memories active or makes one of them active with the other made inactive respectively. In addition, a selection signal generating circuit 46 is provided to control selectors 25-28 by the flag 43 and the lowest bit of an address given from a terminal 44. Then an exclusive OR is secured between the output of the flag 43 and the lowest bit of the terminal 44. Thus the data of a terminal (a) or (b) can be selected. |
