Dummy cell arrangement for an MOS memory.

摘要

A dummy cell arrangement is provided for sensing the logic state of an accessed memory cell (M1) in an MOS memory in which a memory cell capacitor (CM) of a predetermined size is associated with each memory cell. A plurality of dummy cells (D1-D4) are included, each of which has a dummy capacitor (CD) of substantially the same predetermined size as the memory cell capacitor. When the state of an accessed memory cell is to be sensed, its memory cell capacitor (CM) is coupled to a bit line (A) to change the voltage thereon and a selected dummy cell capacitor (CD) is coupled to a pair of bit lines (B, E) so as to effect substantially equal transfers of charge between the dummy capacitor and the bit lines to which it is coupled. The resulting voltage on the memory cell capacitor's bit line (A) is compared to the voltage on one of the dummy capacitor's bit lines (B) so as to determine the logic state of the accessed memory cell.