| 摘要 |
PURPOSE:To generate a dynamic signal which has less power consumption and has less influence upon fluctuation of a power source voltage, by boosting a clock signal input by a boosting circuit due to capacity coupling to generate a delayed clock signal output. CONSTITUTION:When the potential difference of a certain degree is generated between both ends of a capacitor C, a node N2 between a semiconductor circuit 1 and a transistor TRT2 is discharged. Then, the TRT2 and a TRT4 which has the base cascaded to the TRT2 are turned off, and the node N2 is charged from a low potential VL1 to a high potential. By capacity coupling due to the capacitor C, etc. between the node N2 and a node N1 between the circuit 1 and a TRT1, the node N1 is boosted and has a potential Vp higher than a power source voltage VDD. Thus, a clock input signal phi of the circuit 1 is supplied to a node N4 where the drain of the TRT4 and the source of a TRT5 are connected, and a delayed signal phid is outputted. |
