| 摘要 |
A Josephson junction terminated line logic powering scheme is disclosed wherein a logic gate and a regulating gate are utilized in at least a single logic circuit to provide a constant voltage to the logic circuit. The circuit comprises a terminated line logic gate with its associated sense gate and a regulating gate in series with the logic gate. When the logic gate is switched to the voltage state, it sends a disturb signal up and down the line which carries the gate current to the logic devices. A regulator gate which has already been biased to the voltage state is reset to the zero voltage state by the disturb signal. The resetting of the regulator gate sends out a disturb signal which cancels the original disturb signal with a small delay. The result of the combination of the disturbance generated by the logic gate and the regulating gate is an extremely narrow pulse with a maximum width equal to the round trip delay between the adjacent gates having an amplitude of I-Imin. In the steady state, the total voltage drop across the supply line remains constant before and after logic operations. Thus, d.c. regulation problems are eliminated. |
