发明名称 Fail-safe decoder for digital track circuits
摘要 A selected unique digital comma-free code word is transmitted through track section rails from one end and, when received at the other end, is applied serially to a shift register which supplies a parallel readout of shifting pattern to one input of a fail-safe comparator. The second comparator input is selected from the different possible digital code patterns of the track code word stored in a memory device. When inputs are equivalent, the comparator passes an input test signal to its output. Absence of comparator output causes the selected stored code word to be stepped through the stored patterns, in reverse order to track code shift, until equivalence is again obtained. The periodic output signals, of approximately 50% duty cycle, are processed through a series filter-rectifier network, tuned to test and periodic output signal frequencies, to energize a track relay to register an unoccupied track section indication.
申请公布号 US4320881(A) 申请公布日期 1982.03.23
申请号 US19800193765 申请日期 1980.10.03
申请人 AMERICAN STANDARD INC. 发明人 CAMPBELL, RICHARD D.
分类号 B61L1/18;B61L21/06;(IPC1-7):B61L21/00;G08C19/28 主分类号 B61L1/18
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