发明名称 DATA PROCESSOR
摘要 PURPOSE:To realize highly efficient processing, by controlling almost all the processing of an instruction under a hard wired logic system by a controlled flip-flop according to a prescribed sequence, and controlling a complicated processing being a part of the processings, by a microprogram. CONSTITUTION:When an instruction is set to an instruction register from a main memory, an operation code OPC becomes an address of a memory device 2, and its contents are read out. When the instruction is not executed by a microprogram but is executed by a direct control of an F/F group 3, an FF4 is set to ''1'', an output of the memory device 2 is used for initializing the F/F and setting a sequence code, the F/F group is operated in accordance with the order designated by the sequence code, and a control signal for a logical operating circuit (ALU) control and a register (REG) control is outputted. In case when the instruction is controlled by the microprogram, the FF4 is set to ''0'', the head address of the microinstruction is set to a microprogram address register 5, a control memory device 6 is set to a microprogram address register 5, a control memory device 6 is accessed, and a data is read out and processed.
申请公布号 JPS5748137(A) 申请公布日期 1982.03.19
申请号 JP19800121186 申请日期 1980.09.03
申请人 FUJITSU KK 发明人 KAWAKATSU KUNIHIRO
分类号 G06F9/22;G06F9/28 主分类号 G06F9/22
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